Digital receiver for reactive radio

ABSTRACT

A digital receiver is disclosed. In one aspect, the receiver includes a receiving module for receiving packetized data. The receive may further include a first processing module for packet detection having a first programmable processor. The receiver may further include a second processing module for demodulation and packet decoding having a second programmable processor. The receiver may further include a first digital receive controller having a third processor arranged for being notified of detection of data by the first processing module and for activating the second processing module.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of PCT Application No.PCT/EP2007/54770, filed May 16, 2007, which is incorporated by referencehereby in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a digital receiver structure suitablefor a software-defined radio platform.

2. Brief Description of the Related Technology

Software-defined radio (SDR) is a collection of hardware and softwaretechnologies that enable reconfigurable system architectures forwireless networks and user terminals. SDR provides an efficient andcomparatively inexpensive solution to the problem of buildingmulti-mode, multi-band, multi-functional wireless devices that can beadapted, updated or enhanced by using software upgrades. As such, SDRcan be considered an enabling technology that is applicable across awide range of areas within the wireless community.

Handheld digital receiver cost reduction and time-to-market improvementcall for software defined radio (SDR) implementation. To be viable inportable handheld devices, SDR needs to be low power. SDR low cost andlow power requirements implies:

-   -   reactive multi-mode operations: the receiver should be able to        be configured to detect, possibly concurrently, transmission        according to a multitude of communication standards. When those        transmissions are detected, they must be decoded.    -   scalability: multiple versions of the platform, matching demand        and silicon process technology evolution, must be derived from        an initial, scalable design.    -   programmability and retargetability: the development time to        deploy an application based on a SDR platform must be minimized.        This is only possible by implementing integrated        platform-instantiation and application-mapping flows based on        high-level languages.        As programmability and energy efficiency must be carefully        traded off to maintain energy efficiency at the level required        for mobile device integration, programmability may only be        introduced where its impact on the total average power is        sufficiently low or at those places where the resulting extra        flexibility can be exploited to yield an average energy gain        through better matching of the system behavior to the        utilization and the environment.

State-of-the-art solutions tackle multiple standards and future-proofSDR platforms with e.g.:

-   -   master-slave general purpose processor (GPP)—digital signal        processing (DSP) with multiple radio interface,    -   single or homogeneous multi-core System on Chip (SoC),        Power consumption is tackled at computer architecture and/or        circuit level, but not at system level (except for dynamic power        management).

Many different architecture styles have already been proposed for SDR.Most of these are designed keeping in mind the most importantcharacteristics of wireless physical layer processing: high data levelparallelism (DLP) and data flow dominance. For the first characteristic,hybrid VLIW (Very Long Instruction Word) and vector/SIMD (SingleInstruction/Multiple Data) architectures are often considered to exploitthe data level parallelism with limited instruction fetching overhead.However, directly mapping C-code, even with high DLP, on sucharchitectures remains a challenge for the compiler. The secondcharacteristic is exploited by fine-grain reconfigurable arrays (FGA)and coarse grain reconfigurable arrays (CGA). The main bottleneck of theFGAs is the high interconnect cost that hampers their scalability andthat yields significant energy overhead. CGAs improve on this pointproposing less but more complex functional units.

Although several proposals (see e.g. also ‘Finding the optimumpartitioning for multi-standard radio systems’, Bluethgen, Proc. Int'lSDR Technical Conference, November 2005) have contributed significantlyto the integration of SDR in personal communication handhelds, none ofthe proposed platforms has the required features to enable reactiveradio. Specifically, no solution has been proposed for multi-modereactivity. Also their computing power at reasonable energy-efficiencyis still too limited to exploit multiple signalling dimensions. This ismainly due to the fact that only the characteristics of themodulation/demodulation baseband processing are considered. In practice,a radio standard implementation also contains functionalities for mediumaccess control and, in case of burst-based communication, signaldetection and time synchronization. The desired characteristic of datalevel parallelism (DLP) does not hold for medium access control (MAC)processing which is, by definition, control dominated and, hence, betterfits on RISC processors. Besides, packet detection and coarse timesynchronization of burst-based transmission have a significantly higherduty cycle than packet modulation and demodulation. They hence requireanother flexibility/efficiency trade-off.

One possible application of such a reactive digital receiver relates toa mechanism for a hand-over operation between two base stations oraccess points of a mobile terminal comprising such receiver. The basestations are each arranged to cover a particular coverage area or cell.The coverage areas are partly overlapping, such that the arrangementsupports a cellular network.

A hand-over can be a hard hand-over whereby the mobile terminal is(physically) connected to only one base station at a time, so that theconnection to the current base-station must be terminated before theconnection to the new base-station can be achieved. This implies anunconnected period (a “break”) during the hand-over. The hard hand-overis also referred to as “break-before-make”. On the contrary, a softhand-over is a hand-over mechanism where the mobile terminal can beconnected to two base-stations at the same time. This is also called“make-before-break”.

With seamless hand-over is meant a hand-over going by unnoticed from auser perspective, i.e. without interruption of ongoing services.Seamless hand-over does not necessarily imply soft-handover (thoughsoft-handover makes seamless handover easier).

Soft handover is possible between two 3G base stations operating at thesame frequency and distinguished by two different CDMA scrambling codes.In the 3G cellular systems, a scrambling code, associated to each basestation, is super-imposed to the usual CDMA code that separates themobile terminals. One mobile terminal can make use of the scramblingcodes to receive the signals of two base stations simultaneously with asingle front-end.

Seamless hard handover can be achieved through synchronization of thebase stations. Based on this synchronization the base station allows theterminal to scan neighboring cells during a limited time and if neededit triggers a hard hand-over that can happen relatively fast. Thistechnique is not possible for hard hand-over between different networktechnologies on one hand, and requires complex network synchronizationfor a single network on the other hand.

For 802.11 wireless LAN, there is the possibility of connecting oneterminal to multiple access points at the same time, through a timedivision scheme using the power save mechanism provided by the 802.11protocol. This technique is useful for protocols and applications wherethe protocol provides a power-save feature with a time constant smallerthan the latency bound of the application.

In patent application EP1328066-A2 a semiconductor device is disclosedthat is functionally divided into blocks. The power supply systems ofthe blocks are divided into a non-controlled power supply group in whichpower is always on and a cascade of controlled power supply groups ineach of which groups a supply of power can be turned on/offindependently, but in a chained way. This means that the power of agiven block is controlled by the predeceasing block in the cascade. Theblocks that are not necessary for performing a specific piece ofprocessing are not supplied with power. For example, the decoding blockis only switched on when the processing in the preceding demodulationblock has been done. The division into various blocks is purelyfunctional and does not take into account any consideration regardingthe actual static or dynamic power of the blocks, their duty cycle, northeir trade-off between energy efficiency and flexibility. Byconstruction, the higher the hierarchical level of a block, the higherthe duty cycle is.

U.S. Pat. No. 6,978,149-B1 relates to a transceiver the receiver part ofwhich is switchable between a sleep mode and an active mode. A controlcircuit is provided for switching the receiver from sleep mode to theactive mode when an information signal to be received is detected. Thecontrol circuit takes a decision to switch based on a power level of theinformation signal, the power level being represented by a receivedsignal strength indicator (RSSI) signal. Here again, a cascadedactivation chain is foreseen, with a purely functional partitioning.

It is desirable to have a scalable, energy-efficient digital receiverstructure enabling spectrum environment awareness and gradual systemwake-up in response to incoming radio transmissions.

SUMMARY OF CERTAIN INVENTIVE ASPECTS

Certain inventive aspects relate to a digital receiver comprising

-   -   a receiving module for receiving packetized data,    -   a first processing module for packet detection comprising a        first programmable processor,    -   a second processing module for demodulation and packet decoding        comprising a second programmable processor,    -   a digital receive controller comprising a third processor        arranged for being notified of data availability by the first        processing module and for activating the second processing        module.

In a preferred embodiment the receiving module for receiving packetizeddata is an analogue front end.

Advantageously, in use, the power consumption of the first processor islower than the power consumption of the second processor. In use, theflexibility of the first processing module is lower than the flexibilityof the second processing module. Specifically, the instruction set ofthe second processing module is richer and allows usage of high-levellanguage compilers.

Preferably the first processor is an application specific instructionset processor. On the other hand, the second processor advantageously isa general purpose processor.

In a preferred embodiment the first processing module comprises a thirdprocessing module for power level detection and a fourth processingmodule for synchronization. The fourth processing module comprising thefirst processor.

The third processing module is arranged for being fed with packetizeddata from the receiving module for receiving packetized data. The thirdprocessing module is preferably a hardware block.

The digital receiver may further comprise a second controller for thefirst processing module, the second controller being arranged forreceiving at its input notification of power detection from the thirdprocessing module and arranged for activating the fourth processingmodule. The fourth processing module is typically arranged for receivingcontrol signals from the second controller. It further receives datapackets from the receiving module for receiving packetized data via afiltering unit. The second controller is a configurable hardware block.Advantageously the third processing module is arranged for providingsettings for the receiving module for receiving packetized data. Thefirst processor (in the fourth processing module) is preferablyoptimized for correlation.

In another preferred embodiment the digital receiver comprises aplurality of the first processing modules, which advantageously have asame architecture. Preferably at least some of the first processingmodules are arranged for sharing a same bus interface. The receiver maythen further comprise a plurality of receiving modules for receivingpacketized data. Each receiving module for receiving packetized data isthen preferably connected to a corresponding antenna.

In another embodiment, the digital receiver comprises a plurality of thesecond processing modules, having a general purpose architecture or anarchitecture dedicated to specific subparts of thedemodulation/decoding.

The digital receiver is arranged for operating in different modes, eachof the first processing modules being programmable for operating in oneof the modes.

In another embodiment the first processing modules share the secondcontroller. Alternatively, each of the first processing modules has itsown second controller.

Preferably the fourth processing module is arranged for filtering andfurther comprises a first memory for buffering data packets. The firstmemory is preferably a circular data buffer. Advantageously, the fourthprocessing module is further arranged for performing the filteringoperation on a configurable hardware block.

In a further embodiment the digital receiver further comprises a secondmemory for data reception, in parallel to the first memory. The receivermay further comprise transfer module for data transfer between the firstor the second memory on the one hand and memory of the second processoron the other hand. The transfer module for data transfer preferablycomprises a bus and a direct memory access. The bus preferably is ashared bus. Optionally a plurality of busses can be provided, as well asa plurality of direct memory accesses.

In another embodiment the digital receiver further comprises a FEC coderarranged for being fed with data from the second processing module, theFEC coder being arranged for being activated by the first digitalreceive controller.

In a preferred embodiment the digital receiver as previously describedis arranged for processing signals according to any standard of thefollowing: IEEE802.11a, IEEE802.11n, 3GPP-LTE, IEEE802.16e.

Another aspect relates to the use of a mobile terminal comprising adigital receiver as described for establishing a soft hand-over betweentwo base stations of a wireless communication system.

In another aspect, a digital receiver is disclosed. The receivercomprises a receiving module for receiving packetized data, a firstprocessing module for packet detection comprising a first programmableprocessor, a second processing module for demodulation and packetdecoding comprising a second programmable processor, and a first digitalreceive controller comprising a third processor arranged for beingnotified of detection of data by the first processing module and foractivating the second processing module.

In another aspect, a digital receiver is disclosed. The receivercomprises means for receiving packetized data. The receiver furthercomprises means for packet detecting, the detecting means beingprogrammable. The receiver further comprises means for demodulating andpacket decoding, the demodulating and decoding means being programmable.The receiver further comprises means for being notified of detection ofdata by the detecting means and for activating the second processingmodule.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 represents a top level view of the platform architecture.

FIG. 2 represents a top level view of the platform architecture.

FIG. 3 represents a general overview of the architecture of a digitalreceiver according to one embodiment.

FIG. 4 represents a practical implementation of a DFE tile.

FIG. 5 represents the same architecture as in FIG. 3, with a detailedview on block (10).

FIG. 6 represents a possible ASIP architecture for the first processor.

FIG. 7 represents an activity trace when detecting a valid burst.

FIG. 8 represents an activity trace when detecting a false trigger.

DETAILED DESCRIPTION OF CERTAIN ILLUSTRATIVE EMBODIMENTS

In the approach according to one embodiment the power consumption istaken into account from a system perspective. More specifically, itemploys a partitioning selected for obtaining predetermined performancein terms of flexibility and power consumption and hierarchicalactivation with aggressive power management. Such opportunisticpartitioning aims at providing flexibility where and when it is needed.Such targeted flexibility calls for heterogeneous Multi-ProcessorSystem-on-Chip (MPSOC) architectures. The main idea behind hierarchicalactivation is to gradually enable increasingly power-consuming parts ofthe platform to perform a sequence of tasks with increased capability todetect the signal. The gradual wake up capitalizes on a cascade offunctional blocks that are implemented with a monotonically increasingflexibility and hereby decreasing energy efficiency, which iscompensated by the decreasing duty cycle obtained by construction.

With platform is meant the framework on which applications may be run.This comprises a hardware platform System-on-Chip (SoC), hardwareabstraction layer software, tools to get application software mapped onthe platform System-on-Chip (SoC) and possibly application softwarelibraries. In the following the focus is on the HW platform SoC.

Parts of the application that have low duty cycle can be groupedtogether to be mapped to highly flexible hardware. The cost offlexibility is then well amortized by implementing the aggressive powermanagement exploiting the low duty cycle. For parts having a higher dutycycle and therefore a higher impact on the average power, less flexibleapplication-specific hardware are required. Parametrizable hardwareblocks or multiple specialized cores are pragmatic solutions. Within thepart to be targeted to programmable/reconfigurable hardware, asub-partition can be achieved between control-dominated tasks (lownumber of operations per control branch) and computation- and/ortransfer-dominated tasks. The former are later targeted to scalarmicro-architecture, the latter being candidate for instruction-levelparallel micro-architecture. Finally, the degree of data levelparallelism and the operation per memory ratio are used to decide ifmultiple flavors of those architectures must be consideredsimultaneously. From this partitioning, one can extract the top-levelplatform architecture defining the number and type of cores.

The digital receiver can be subdivided in a number of building blocks.FIG. 1 depicts a top level view of the considered platform template. Thehigh level platform architecture may comprise various cores: multipledigital front-end cores assigned to signal detection and interfacingwith analogue front-end, multiple baseband engines assigned to signalmodulation/demodulation and multiple antenna processing, outer modemtiles assigned to FEC coding/decoding and a core for platform controland medium access control.

A digital front-end associated to the analogue front-end is provided forradio signal scanning, analogue front-end steering (e.g. automatic gaincontrol (AGC)), short-loop analogue front-end control, I/Q sampleinterfacing, packet detection, decimation and burst pre-synchronizationin receive mode and signal interpolation in transmit mode. Thosefunctions are characterized by a relatively high duty cycle. The DFEpower is therefore critical.

The remaining modem functionalities are split into two groups. Basebanddigital signal processing units implement receive functions relative tofine synchronization, front-end impairment compensation, multi-antennaprocessing and demodulation. In transmit mode, channel encoding andmodulation are implemented on the baseband units too. The consideredprocessor architecture is based on a hybrid SIMD-CGA approach. Forwarderror correction engines accelerate the data (de)coding from the(de)multiplexed streams (outer modem). The former iscomputing-intensive, with high data-level parallelism and is dominatedby saturated fixed-point complex number manipulations. The basebandprocessor architecture can be one with multiple baseband cores. Thearchitecture may comprise programmable and/or reconfigurable hardwareblocks, possibly containing a plurality of (parallel) cores. A scalableinterconnect may be provided between the various cores. The interconnectmay be a segmented bus interconnect (see next paragraph for moredetails). The second group of functionalities is transfer-intensive andoften requires special arithmetic. Both have reasonably low duty-cyclein application scenarios. Finally, medium access control (MAC) andcognitive control processing are both transfer- and control-dominatedwith low duty cycle. They hence form a fourth partition. The platformcontrol and media access control can be carried by a general purposecore (e.g. an ARM9 processor).

As already mentioned, the scalable interconnect (see FIG. 1) mayadvantageously be a segmented bus interconnect. FIG. 2A shows a possibleimplementation. The segmented bus architecture comprises two single-portdirect memory access controllers (DMAC) with an adjustable FIFO depth.Note that in FIG. 2 MM means main memory, DFE digital front-end, BBEbaseband engine and FECE forward error correction engine. A burst lengthof 16-word gives a reasonable trade-off between throughput and latencyas the increased burst length introduces extra delay for the access ofthe lower priority transfer. As both DMACs need to have access to thebus segments to perform back to back parallel data transfers, a suitablebus connectivity must be provided. A multi-layer AHB bus (Amba HighPerformance Bus) as shown in FIG. 2A is provided. The concurrency ofmultiple 16-word burst transfers between the two segments is shown inFIG. 2B. The throughput of the segmented bus of FIG. 2A can amount to4.3 Gbit/s, which is sufficient for e.g. IEEE802. 11n processing. Thebus utilization may amount up to more than 50%, preferably to more than60% and even more preferably to more than 65%. For completeness it isrecalled that a transaction on a AHB bus consists of an address phaseand a subsequent data phase (without wait states: only two bus-cycles).Access to the target device is controlled through a multiplexer(non-tristate), thereby admitting bus access to one bus-master access ata time. The AHB bus allows (among other features) for burst transfers,pipelined operations, several bus masters, single-cycle bus masterhandover, non-tristate implementation and large bus-widths (64/128 bit).

Programmable solutions intrinsically suffer from higher powerconsumption when compared to dedicated solutions. In the proposedplatform, the scalable digital front-end comprises multiple ‘tiles’,which, as already mentioned, implement signal detection andpre-synchronization functions. These multiple tiles require both veryhigh energy efficiency and sufficient programmability to implementdetection of different standards on the same tile. The digital front-endof the scalable, energy-efficient digital receiver has a flexibledetection/time synchronizer unit allowing for major savings in theaverage power consumption of the platform by supporting a gradualwake-up of the system in response to incoming radio transmissions.

In general terms the digital front-end is the part of the system that:

-   -   proceeds to the tasks needed in stand-by mode while the rest of        the platform is shut off, namely signal detection and/or        scanning,    -   generates the interrupts to wake up the platform if one or        several signals are detected,    -   buffers the received rough data during the wake-up sequence of        the platform,    -   ensures automatic gain control (AGC), RX filtering, and coarse        synchronization when one or several stream(s) is(are) received,    -   ensures TX filtering if one or several streams are transmitted.

The digital front-end (DFE) is the signal entry/exit point of thereactive radio platform. It is connected to one or multiple RFfront-end/antenna sections via an analogue front-end. To minimize itsoverall power consumption its flexibility is kept to a minimum.Commonalities between most digital radio schemes are exploited to derivea generic architecture. Due to the versatility of synchronizationalgorithms across digital radio standards, flexibility is still requiredfor the synchronization section. An application specific processor withspecific support for autocorrelation and crosscorrelation is considered.

FIG. 3 presents a generic overview of the digital front-end architecturefor one detector tile (corresponding to one antenna). FIG. 4 shows anexample of a possible practical implementation. A single tile containsthe digital receive and transmit logic to interface to a single antenna.

Incoming packetized data are input to a first processing module (10)(this term is used in this description as a synonym for ‘detectortile’). This first processing module (10) is in connection with anantenna section (95) via an analogue front-end (90). Data detection bythe first processing module is signalled to a digital receive controller(30). This controller (30) is arranged for copying the available datafrom the first processing module memory towards a second processingmodule memory and activating a second processing module (50), whichtakes care of demodulating and decoding the packets of data. Thedetector tile (10) comprises a first processor (15), preferably anapplication specific instruction set processor (ASIP). The secondprocessing module (50) comprises a second processor (55), typically ageneral purpose processor. It is to be noted that the data flow does notpass through the controller (30). Data copy is done by direct memoryaccess over the system bus.

The transmitter part of a DFE tile includes or consists of a buffer anda VLSI interpolation filter. A start command can be issued allowing thesamples to be clocked out towards the analog front-end through thefilters. The transmit (TX) buffers (see FIG. 4) have a programmablethreshold that triggers an interrupt once the number of availablesamples falls below this threshold. This interrupt is handled by theplatform controller.

The receiver part of the DFE tile in FIG. 4 contains a chain made of theVLSI decimation filters, the buffers and compensation units for DCoffset and carrier frequency offset (CFO). Next to the data path, twodedicated micro-processor cores are implemented. The first handles thefront-end automatic gain control (AGC) and the DFE power management. Thesecond core is optimized for time synchronization.

FIG. 5 shows a more detailed view on the architecture. The data path ofthe DFE from a certain antenna is such that the unfiltered samples inthe data packets are analyzed by a third processing module (12). This istypically an AGC controller that will calculate the correct settings forthe front-end (filters etc. . . . ). The third processing module isimplemented as a hardware block.

In a preferred embodiment the digital receiver further comprises aresource activity controller (20) for the first processing module (10)to which the detection of power by the third processing module and/orthe success of data synchronization by the fourth processing module aresignalled. The resource activity controller (20) controls which parts ofthe DFE are activated at a certain point in time, based on the inputsprovided by those different blocks to support gradual wakeup of theplatform. The controller (20) may be a configurable hardware block. Theresource activity controller (20) is capable of activating a fourthprocessing module (16) and of generating a message to wake-up thedigital receive controller. This fourth processing module (16) alsobelongs to the first processing module (10). In one embodiment thisfourth processing module (16) does not receive input from the thirdprocessing module (12). The data paths in the third (12) and the fourth(16) processing modules are in parallel.

It is this fourth processing module (16) that receives control signalsfrom the second controller (20). The fourth processing module (16) alsoreceives data packets from the receiving module of receiving packetizeddata. The fourth processing module (16) comprises the first processor(15). It also comprises a filtering module (17). The output of thereceive filters (17) is stored in a data buffer (18). This is necessary,as the data needs to be buffered while the first processor (15) performsthe coarse synchronization algorithm on the filtered samples. Theprocessor (15) can be connected to the data buffer or to a replica ofthis data buffer, depending on the implementation choices. Further,there is the connection from the data buffer to the main data busthrough a system bus interface.

In one embodiment of the invention the described data path is duplicatedas many times as there are antennas in the system, each antenna havingits own receiving module (90) for receiving packetized data, preferablybeing an analogue front-end as already mentioned. Each tile (firstprocessor module 10) may then have the same architecture. The multipledetection tiles allow a flexible support for MIMO reception and/ormulti-mode scanning. The detection can then be performed simultaneouslyfor different modes. Flexible time synchronization is performed in thefirst processor in each tile. The tile configuration and (hierarchical)activation can be performed by a shared global resource activitycontroller (20). Alternatively, a dedicated resource activity controllercan be provided for each tile separately.

In such an embodiment with a plurality of detection tiles the digitalreceiver can be configured for operating in different modes, wherebyeach detection is programmed for operating in one of the possible modes.

The digital receiver system is made up of a processing hierarchy(including the DFE units and the baseband processors) and a controlhierarchy (made of one or several DFE/resource activity controller(s)).The data may flow straight from the input interface todownsampler/anti-aliasing filter to the circular buffer andsynchronization processor scratch path and then, depending on synchropointer to the baseband processor memory. The data does not flow to theplatform controller, nor to the AGC, nor to the resource activitycontroller.

The blocks of the third and fourth processing module are now describedmore in detail.

The basic idea of the architecture is to keep the main data path asstraight-through as possible. This means that it should be possible topass the input samples that come out of the receive filter (17) to therest of the system without requiring explicit action from the firstprocessor (15). The proposed architecture takes this into account.

The purpose of the AGC controller is to steer the amplification of thefront-end and to detect a possible incoming signal. In case of certainworking modes the AGC controller needs to be by-passed, since signaldetection will only be possible after e.g. a coarse synchronizationoperation or a despreading operation. The default working mode of thethird processing module (12) can be detailed as follows. When the AGC isin free-running mode (default mode on start-up), it starts measuringpower and steers the front-end amplification chain to reach a maximumSNR. The amplification table (optimal gain distribution) is depending onthe front-end used. The power measurement is performed in multiplesteps. Normally there is a power exploration performed followed by finepower estimation. The power estimation itself is an averaging over theincoming samples. When the incoming power reaches a certain threshold,the AGC controller will signal this, enabling a time synchronization.During this time, the AGC is put in hold mode, allowing the timesynchronization in the fourth processing module (16) to find a possiblestart of packet. If the time synchronization doesn't find a start ofpacket, or when the packet transmission has ended, the AGC will go intofree-running mode again. The AGC release signal can come from a failedtime synchronization or an end of packet.

The receive anti-aliasing filters (17) perform the downsampling on theincoming signal. They are heavily power-optimized.

The first processor (15) is preferably an application specificinstruction set processor (ASIP), as previously explained. The so-calledsynchronization processor (i.e. the first processor) is provided withthe filtered data samples that have to be analyzed to determine thecoarse synchronization point. The synchronization processor starts itssynchronization search on the incoming data in reaction to an ACG lockevent. Once it detects a valid synchronization sequence, it interruptsthe host controller and passes the start address of the data in thecircular buffer to the platform controller. The controller cansubsequently start burst transfers of data from the circular bufferthrough the bus slave interface to the other base band processing partsof the system.

FIG. 6 shows a possible architecture of such an ASIP for performingcoarse time synchronization. It has a two-issue VLIW architecture.Besides the traditional Arithmetic Logic Unit (ALU), pipelined complexnumber arithmetic multiplier (MUL), control (CTRL), branching (BRANCH),load and store (L/S) functional units, are present. Besides, threespecific units are added to implement explicit register move and vectorpacking/unpacking. They are specifically: V_ext_vvv_ex, packing twovectors together; S_ext_vrr, unpacking a vector into scalar registers;S_ext_rrv, packing scalars into a vector.

The resource activity controller (RAC) controls what parts of the DFEreceive path are activated at each point in time. It is a registerconfigurable hardware block. The RAC takes decisions based on the inputsignals generated by the AGC controller, the synchronization processorand the platform controller. When e.g. a certain AGC asserts the RXenable signal, the RAC will activate the filter, buffer, and ASIP clockfor the corresponding detector tile. Exceptions to this behavior arewhen operating modes are selected where the ASIP first needs to run acertain algorithm. In this case the complete detector tile is activated,regardless of the status of the AGC. The RAC furthermore take care ofreleasing the AGC from hold mode. It therefore depends on informationgenerated by the synchronization processor (in case of a false AGCtrigger), or the digital receive controller (in case of an ‘end ofpacket’).

One possible way to perform the (de)activation is to use clock gatingand memory substrate biasing in sleep mode. The activation firstrestores nominal bias to the memories (so that they can be accessed atnormal speed at cost of leakage). Then the core is clocked again. Forprocessors, a small wake-up block (always clocked) catches the wake-upsignal for the wake up process. Processors can deactivate themselves bya specific instruction.

The bus interface provides the digital receive controller with access tothe data buffers of the different detector tiles. Through the interface,the controller can perform burst data transfers from the data buffers tothe rest of the system.

The default working principle of the DFE RX subsystem is the following:

-   -   The AGC controller monitors the output of the front-end. The        downsampler/filter is not activated so the data is blocked. If        it detects a possible incoming signal, it notifies the RAC of        this event.    -   The RAC enables the receiver filters, the circular data buffer        and the synchronization processor. The latter will start looking        for synchronization or correlation sequence, depending on the        selected working mode. The synchronization processor hereby        looks for a data preamble (start of a packet) in its memory,        which is in sync with the circular buffer.    -   If the ASIP decides that valid information is present in the        data buffer, it interrupts the platform controller and passes        the correct start address of the data in the circular buffer to        the controller.    -   The controller can then initiate a transfer from the circular        buffer through the bus interface to whatever part of the FLAI        platform that can process the data. The synchronization        processor does not need to take any action in this. For example,        the controller can copy the data from the DFE buffer to the        baseband processor memory, wake up the baseband processor and        instruct it about which functions have to be carried out. When        the baseband processor has finished, it notifies the platform        controller that the data can be copied to the FEC processor        memory and wake-up/notify the latter. Note that by ‘copying’ is        not meant that the data flows through it. It is in fact based on        direct memory access.        The detection tiles, except the AGC controller, can        independently be set in sleep mode when no signal is detected by        the AGC.

As already mentioned, the digital receiver as disclosed above may bearranged for processing signals according to various standards, likee.g. IEEE802.11a, IEEE802.11n, 3GPP-LTE, IEEE802.16e.

As an example, FIG. 7 illustrates the sequence of operations required toguarantee the detection and pre-synchronization of a valid burst for the802.11 a case. The AGC_enable signal is high when the DFE tile isactive. The AGC controller is continuously analyzing the incoming data.Power detection is signalled by AGC_done (on time index 18025 ns in theexample shown). This yields the assertion of the sync_enable,filter_enable and buffer_enable signals that activate respectively thesynchronization processor, the decimation filters and the data FIFO. Forthe considered input signal, a synchronization event occurs at timeindex 27675 (sync) signal. This causes the assertion of a platform levelinterrupt (DFE_int), which wakes up the platform controller. The powerstate flow is appended to FIG. 7. Summing up the state power multipliedby the state duration, one can easily compute the energy consumed duringthe burst detection. Specifically, we consider the energy spent betweenthe reception of the first valid sample until the generation of theDFE_int interrupt. In the current experiment, this gives 228 nJ.

Similarly, the sequence of operation occurring at the reception of ablocker signal (false trigger) is depicted in FIG. 8. Although anAGC_done signal is generated and the filter, buffer and synchronizationprocessor are activated, no synchronization point is found and hence,the ‘sync’ signal is not asserted. Filter, buffer and synchronizationprocessor are forced back to sleep mode after a time-out occurs at timeindex 31025 ns. The state flow is again appended to FIG. 8 and theenergy spent in the false trigger event is computed similarly, giving300 nJ. The average power during the false trigger event is 15.2 mW.Therefore, in field operation where false trigger occurs withprobability p, the consumption of the DFE tile would hence be1.1(1−p)+15.2p mW.

The attention is now drawn to the design of the platform System-on-Chip.The cores micro-architecture and interconnect being known, an ElectronicSystem Level (ESL) platform model based on instruction-set simulators,cycle-accurate interconnect models and behavioral models for theparametrizable cores can be assembled. It is used as reference for thedevelopment and integration of the SDR software and partly as test benchfor the gradual refinement of the platform hardware. Software andhardware development can then be decoupled.

The virtual platform design is a key step in the high level methodologydesign flow. It aims at assembling a platform simulator at a level ofabstraction fitting both for software development (platform control API,functional physical layer, functional medium access control and datalink API) and as reference for platform hardware design. Translationbetween different levels of abstraction is done via so-calledtransactors. This enables executable models with parts at differentlevel of abstraction. The development of the virtual platform mainlyconsists of the development of the IP core models, the optimization ofthe interconnection and execution control/handshaking subsystems and theplatform model integration. A significant part of the platformintegration is the determination of the memory map.

By way of example, a particular application wherein the digital receiveras described herein can advantageously be used, is now given. Theapplication relates to a case of a seamless hand-over of a mobileterminal with two or more antennas between two base stations or accesspoints not synchronized in time and operating at a different frequency(with identical standards or not). The base stations may advantageouslyapply Multiple Input-Multiple Output (MIMO) communication schemes thatpossibly support high mobility of the terminal.

The proposed solution enables seamless hand-over between two basestations of a different network technology (inter-mode handover) as wellas between two base stations operating in the same standard but usingdifferent carrier frequencies.

As the digital receiver structure as presented above enables a flexibleallocation of resources (antennas+analogue front-ends) to differentcommunication modes, it allows optimizing the overall communicationperformance according to the user needs/communication conditions,provided that a smart controller leads the resource allocation. One ofthe antennas of the mobile terminal can be used to scan and initiateassociation to the new base station, while other antennas are still usedto communicate with the current base station, thus enabling softhandover. The quickly switchable and/or reconfigurable blocks in thereceiver support communication whereby the terminal antennas areexploited for communication with at least one antenna less in case atleast one antenna is used for hand-over scanning.

In order to switch from a dual-antenna operation to a single antennaoperation in one network, the base station should be informed of thereduced capacity/reliability of the link. For example, spatiallymultiplexed streams could not be supported anymore, the constellationand/or coding rate could be changed to ensure a given communicationquality.

The application of the digital receiver of the foregoing embodiments fora soft hand-over application illustrates the beneficial effect wherebythe same hardware blocks can be reused.

The foregoing description details certain embodiments of the invention.It will be appreciated, however, that no matter how detailed theforegoing appears in text, the invention may be practiced in many ways.It should be noted that the use of particular terminology whendescribing certain features or aspects of the invention should not betaken to imply that the terminology is being re-defined herein to berestricted to including any specific characteristics of the features oraspects of the invention with which that terminology is associated.

While the above detailed description has shown, described, and pointedout novel features of the invention as applied to various embodiments,it will be understood that various omissions, substitutions, and changesin the form and details of the device or process illustrated may be madeby those skilled in the technology without departing from the spirit ofthe invention. The scope of the invention is indicated by the appendedclaims rather than by the foregoing description. All changes which comewithin the meaning and range of equivalency of the claims are to beembraced within their scope.

1. A digital receiver comprising: a receiving module for receivingpacketized data; a first processing module for packet detectioncomprising a first programmable processor; a second processing modulefor demodulation and packet decoding comprising a second programmableprocessor; a first digital receive controller comprising a thirdprocessor arranged for being notified of detection of data by the firstprocessing module and for activating the second processing module. 2.The digital receiver as in claim 1, wherein the receiving module forreceiving packetized data is an analogue front end.
 3. The digitalreceiver as in claim 1, wherein, in use, the power consumption of thefirst processor is lower than the power consumption of the secondprocessor.
 4. The digital receiver as in claim 3, wherein, in use, thepower consumption of the first processing module is lower than the powerconsumption of the second processing module.
 5. The digital receiver asin claim 1, wherein the first processor is an application specificinstruction set processor.
 6. The digital receiver as in claim 1,wherein the second processor is a general purpose processor.
 7. Thedigital receiver as in claim 1, wherein the first processing modulecomprises a third processing module for power level detection and afourth processing module for synchronization, the fourth processingmodule comprising the first processor.
 8. The digital receiver as inclaim 7, wherein the third processing module is arranged for being fedwith packetized data from the receiving module for receiving packetizeddata.
 9. The digital receiver as in claim 7, wherein the thirdprocessing module is a hardware block.
 10. The digital receiver as inclaim 7, further comprising a second controller for the first processingmodule, the second controller being arranged for receiving input fromthe third processing module and arranged for activating the fourthprocessing module.
 11. The digital receiver as in claim 10, wherein thefourth processing module is arranged for receiving control signals fromthe second controller.
 12. The digital receiver as in claim 10, whereinthe second controller is a configurable hardware block.
 13. The digitalreceiver as in claim 7, wherein the third processing module is arrangedfor providing settings for the receiving module for receiving packetizeddata.
 14. The digital receiver as in claim 1, wherein the firstprocessor is optimized for correlation.
 15. The digital receiver as inclaim 1, the receiver comprising a plurality of the first processingmodules.
 16. The digital receiver as in claim 15, wherein at least twoof the plurality of the first processing modules are arranged forsharing a same bus interface.
 17. The digital receiver as in claim 15,wherein the plurality of first processing modules have a samearchitecture.
 18. The digital receiver as in claim 15, the receivercomprising a plurality of receiving modules for receiving packetizeddata.
 19. The digital receiver as in claim 18, wherein each receivingmodule for receiving packetized data is connected to a correspondingantenna.
 20. The digital receiver as in claim 15, the digital receiverbeing arranged for operating in different modes, each of the firstprocessing modules being programmable for operating in one of the modes.21. The digital receiver as in claim 15, wherein all the firstprocessing modules share the second controller.
 22. The digital receiveras in claim 15, wherein each of the first processing modules has its ownsecond controller.
 23. The digital receiver as in claim 7, wherein thefourth processing module is arranged for filtering and further comprisesa first memory for buffering data packets.
 24. The digital receiver asin claim 23, wherein the fourth processing module is arranged forperforming the filtering operation on a configurable hardware block. 25.The digital receiver as in claim 23, wherein the first memory is acircular data buffer.
 26. The digital receiver as in claim 23, furthercomprising a second memory for data reception, in parallel to the firstmemory.
 27. The digital receiver as in claim 1, further comprising atransfer module for data transfer between the first or the second memoryon the one hand and memory of the second processor on the other hand.28. The digital receiver as in claim 27, wherein the transfer module fordata transfer comprises a bus and a direct memory access.
 29. Thedigital receiver as in claim 28, wherein the bus is a shared bus. 30.The digital receiver as in claim 28, the receiver comprising a pluralityof buses.
 31. The digital receiver as in claim 30, the receivercomprising a plurality of direct memory accesses.
 32. The digitalreceiver as in claim 1, further comprising a FEC coder arranged forbeing fed with data from the second processing module, the FEC coderbeing arranged for being activated by the first digital receivecontroller.
 33. The digital receiver as in claim 1, the receiver beingarranged for processing signals according to one or more of thefollowing group of standards: IEEE802.11a, IEEE802.11n, 3GPP-LTE, andIEEE802.16e.
 34. Use of a mobile terminal comprising a digital receiveras in claim 1, for establishing a soft hand-over between two basestations of a wireless communication system.
 35. A digital receivercomprising: means for receiving packetized data; means for packetdetecting, the detecting means being programmable; means fordemodulating and packet decoding, the demodulating and decoding meansbeing programmable; and means for being notified of detection of data bythe detecting means and for activating the second processing module.